The present invention relates to DMA (Direct Memory Access) controllers for controlling direct data transfer between memories and, more particularly, to a DMA controller providing high efficiency of data transfer and low power consumption.
In a data processing apparatus in which plural devices or memories are connected to a data bus, when performing direct data transfer between the devices or memories, plural DMA transfer requests assigned with priorities are continuously executed to improve the transfer efficiency. There have been known several methods of the DMA transfer, as follows.
For example, Japanese Published Patent Application No. Hei.09-223102 discloses a direct memory access controller (DMA controller) that improves the data transfer efficiency as described above. FIG. 27 is a block diagram illustrating the DMA controller, and FIG. 28 is a block diagram illustrating a data processing apparatus including the DMA controller shown in FIG. 27 as one of components. With reference to FIGS. 27 and 28, in a DMA controller 10022, control data for plural DMA transfers are set in registers (data holding means) 10012xcx9c10016, a DMA wait register (priority holding means) 10027 holds the priorities of the plural DMA transfers, and the plural DMA transfers are executed in the order of the priorities held by the DMA wait register 10027, under control of a control circuit (transfer control means) 10025. In the DMA controller 10022, the control circuit 10025 is connected to a CPU 10004 through a DMA access line 10023. Through the DMA access line 10023, addresses, data, and a control signal for access of the CPU 10004 to the registers 10012xcx9c10016 are transferred, and an interruption signal, a request signal, and an acknowledge signal for informing the end of DMA transfer or the like are transferred. The priorities stored in the DMA wait register (priority holding means) 10027 are predetermined on the basis of the input times of the control data of the plural DMA transfers, or the importance of I/O units 10007 as destinations.
Further, there have been known several methods of clock control to realize low power consumption in a data processing apparatus.
For example, Japanese Published Patent Application No. Hei.08-255034 discloses a low power consumption type data processing apparatus that reduces power consumption without changing the design of a control circuit of a LSI as a whole. The construction of this low power consumption type data processing apparatus is shown in FIG. 29. The data processing apparatus comprises a plurality of functional circuits 30123xcx9c30125, clock control gate circuits 30117xcx9c30119 provided for the respective functional circuits, gate control registers 30105xcx9c30107 for recording control data that define the operations of the respective gate circuits, and an address decoder circuit 30111 for controlling writing of data into the registers 30105xcx9c30107. The registers 30105xcx9c30107 are allocated to memory map areas of a CPU or the like, and have their own addresses. The address decoder circuit 30111 decodes address values of the respective registers, which are supplied through the address bus 30103, on the basis of a write enable signal Sen inputted to the circuit 30111, according to a command from the CPU, and records the control data to the functional circuits, which are supplied through the data bus 30104, in the registers. The outputs from the registers are used as clock supply control signals Scc for the respective functional circuits 30123xcx9c30125, and the gate circuits 30117xcx9c30199 permit or inhibit supply of clock signals to the functional circuits 30123xcx9c30125, on the basis of the clock supply control signals Scc.
Meanwhile, Japanese Published Patent Application No. Hei.08-153387 discloses a FIFO memory that inhibits access according to the number of significant pixels of an input video signal to realize low power consumption. The construction of the FIFO memory is shown in FIG. 30. FIG. 30 is a block diagram illustrating the FIFO memory in view of its function. The FIFO memory comprises a memory cell array 40006 into/from which a data signal is written and read; a clock generator 40003 that receives a reset signal RES supplied from the outside, and generates a CLK (bit line clock) for an I/O circuit 40007 and a first clock CLK1 (word line clock) for a word line pointer 40004, on the basis of a clock signal CLK0 supplied from the outside; an address designation means (the I/O circuit 40007 and the word line pointer 40004) that makes access to the word lines and the bit lines of the memory cell array 40006 on the basis of the CLK and the CLK1, respectively; and a control flag generator 40002 that generates a signal to stop the operation of the clock generator 40003. According to the CLK1 outputted from the clock generator 40003, the word line pointer 40004 sequentially designates the word lines 40008. When the final pointer 40005 outputs a last line access signal PAS3 indicating access to the last word line 40008E, to the control flag generator 40002, the control flag generator 40002 detects the access of the last address on the basis of the last line access signal PAS3 and a clock COS that is in synchronization with the CLK1, and outputs a clock control signal CCNT to the clock generator 40003 according to the timing of the detection. On receipt of the clock control signal CCNT, the clock generator 40003 stops counting of the fundamental clock CLK0. That is, the FIFO memory is a special FIFO memory provided with a clock control signal generation means (control flag generator 40002) which detects the timings to start writing and readout of data from the control signal, starts supply of the clock to the memory cell array 40006, and detects the last address signal designated by the address designation means (the I/O circuit and the word line pointer) to stop the clock of the clock generator 40003.
Furthermore, Japanese Published Patent Application No. Hei.7-182857 relates to a microcomputer system, and discloses a method of performing self-refresh control on a DRAM at waiting of a CPU. FIG. 31 is a block diagram illustrating the construction of the microcomputer system.
With reference to FIG. 31, when the microcomputer system is set in the waiting state, a self-refreshing mode is set by a CPU 50001, and switching is performed from an interval refreshing circuit 50004 to a self-refreshing circuit 50005 by a command from a RAM controller 50003. Then, under the state where a clock signal to be generated from a clock generator 50002 during normal operation is stopped, the self-refreshing circuit 50005 supplies a control signal to the DRAM controller 50003 to make the DRAM controller 50003 perform self-refreshing.
Furthermore, Japanese Published Patent Application No. Hei.7-169266 discloses a method of performing split control on a memory cell array in a semiconductor memory device. FIG. 32 is a block diagram illustrating a fundamental structure of a semiconductor memory.
With reference to FIG. 32, the semiconductor memory is provided with a plurality of memory arrays 60001, and when a predetermined memory array 60001 is selected by a memory array selection circuit 60005, a word line in the selected memory array 60001 is selected according to an address of a first external address signal group. Simultaneously, with respect to the memory arrays 60001 which are not selected, a word line fundamental clock for self-refreshing and a word line fundamental clock for refreshing (/RASF) are outputted from a clock generation circuit 60006 for self-refreshing that is contained in the chip, to select word lines in the unselected memory arrays 60001. Before a set time at which the memory array 60001 is to be selected, a refreshing stop signal is outputted to stop the refreshing operation compulsorily, whereby re-storage of sufficient charge in the memory cells is avoided. Since the memory array is so divided and the selected memory array performs normal read/write while the unselected memory arrays perform refreshing, there is no competition between normal read/write and refreshing in one memory array and, therefore, it is not necessary to control refreshing from the outside, and high-speed serial access is achieved. Further, the memory array selection circuit 60005 is used to select at least one memory sell array, and a selection signal from this circuit 60005 is used to select either the output of the word line fundamental clock (/RAS) or the output of the clock for refreshing (/RASF).
In the DMA controller described in Japanese Published Patent Application No. Hei.9-223102, however, since data transfer is executed at the time when the control data of plural DMA transfers are set, the control data cannot be set in advance, and data transfer requests cannot be reserved in advance. Therefore, setting of plural data transfers cannot be performed in advance according to a program of the CPU or the like, whereby the degree of freedom in program design of the CPU or the like is reduced.
Further, in the DMA controller, the priorities are not designated arbitrarily but are designated according to the control data setting times or the importance of the I/O units as destinations. Therefore, when the importance of the destination I/O units varies, the priorities cannot be set arbitrarily. Further, as means for holding the plural transfer data, the priorities of the transfer data are stored. Therefore, when the I/O units as destinations increase, the priority holding means should be increased by the increase of the I/O units.
Further, in the data transfer request process described in Japanese Published Patent Application No. Hei.9-223102, the order of data transfer requests is determined as soon as the requests are accepted. Therefore, interruption/resumption of data transfer, which is complicated, may be required, whereby the priorities may be inverted depending on the timings of data transfer requests and the priorities. That is, in the case where the priorities of reservations are determined at the time of data transfer requests, if a data transfer request which has been made recently but has a higher priority is received before starting the next data transfer, the order of execution of data transfer cannot be changed. That is, the order of data transfer cannot be optimized.
Further, although the DMA controller described in Japanese Published Patent Application No. Hei.9-223102 can realize interruption of data transfer, it cannot realize canceling of data transfer request being reserved, or rearrangement of data transfer requests being reserved, by a program of the CPU or the like. Further, in order to cancel data transfer being executed, this DMA controller employs a method of temporarily stopping DMA transfer while the data bus is released for the CPU, but it does not employ a method of stopping DMA transfer being executed to start new DMA transfer. In order to realize such interruption or temporal stop of DMA transfer, means for holding data for resuming the DMA transfer is required and, further, periods for holding the data and resuming the DMA transfer are required, resulting in complicated control and circuit construction. Considering that the control and circuit construction are complicated, the conventional method provides less effect unless the number of residual data transfers at interruption is larger than the number of cycles of (data saving process+transfer resuming process). Further, even though the possibility that the DMA transfer is interrupted or temporarily stopped is very low, the device circuit is increased in scale and complicated, resulting in disadvantages in time period for development and power consumption.
Furthermore, in Japanese Published Patent Application No. Hei.9-223102, since DMA transfer is executed at the time when control data or a data transfer request is issued, it is impossible to reverse data transfer in advance and execute the data transfer automatically when a predetermined time comes, or at a predetermined timing. Further, since the data holding means is divided into plural parts, access control for each part is required, whereby the device construction is increased and, moreover, plural access commands must be issued by the program of the CPU or the like. Furthermore, this prior art literature describes that the above-mentioned data holding means holds address information and I/O (destination) information. However, since these information should be divided into plural resources when being stored, even when various access patterns are desired when making access to the memory, only one pattern access is realized because the data holding means does not hold parameters relating to these information.
When there are plural data transfer request sources, the priorities should be held for the respective destinations as described in Japanese Published Patent Application No. Hei.9-22310. However, since the number of transfer request sources is not always equal to the number of destinations, if the number of destinations increases as the number of transfer request sources increases, the number of holding means increases in the prior art method. Further, since both of the priorities and the entry order should be checked in the data transfer process, control is complicated.
Further, with respect to the prior art clock control system that realizes low power consumption, when performing clock supply/stop control by the prior art apparatus described in Japanese Published Patent Application No. Hei.8-255034, since access to the control register should be made before and after the functional circuit is operated, accurate control by the program of the CPU or the like is required.
Further, in the FIFO memory disclosed in Japanese Published Patent Application No. Hei.8-153387, although the clock control method for the memory cells is described, such control as described in this literature is not incorporated in memory devices that are generally used as parts, and therefore, the memory cells must be controlled by an external controller. Since the external controller is provided with a memory controller, the controller must perform low-power-consumption control including the memory controller. Accordingly, the timing to start data transfer cannot be detected by a reset signal at the access start time to the memory as described in the prior art method, when plural pieces of data transfer requests are reserved in advance, or when the memory access pattern is arbitrary, or when the number of times of data transfer or the number of data transfers is arbitrary, or when there are plural and arbitrary timings to start data transfer. Further, also the end of data transfer cannot be detected by detecting the last word line access. Further, since the number of reserved data transfer requests and the number of transfers are arbitrary, these cannot be set in advance. Moreover, when there is only one memory to be accessed, clocks are supplied to the non-accessed area in the memory, resulting in waste of power. Furthermore, when the memory is constituted by a DRAM, even if a part of the DRAM is accessed, the whole DRAM should be operated at each access, and the whole DRAM should be operated also at refreshing, resulting in waste of power.
Furthermore, in the apparatus disclosed in Japanese Published Patent Application No. Hei.7-182657, since the self-refreshing mode control circuit is selected only when the system is in the waiting state, the setting cannot be arbitrarily changed in real time during operation, and therefore, the power at operation cannot be reduced. Further, when the DRAM is divided into plural banks, how to control them is not described. Further, in the case where the DRAM is divided into plural banks, when automatic refreshing is performed on unused banks, clocks must be supplied to the unused banks, resulting in waste of power. Moreover, the data forfeits if no clock is supplied.
Furthermore, the semiconductor memory disclosed in Japanese Published Patent Application No. Hei. 7-169266 should be fabricated by changing the construction of the semiconductor memory itself, leading to high cost. Further, since each memory cell array 60001 is provided with an address selection circuit 60003, a row decoder 60002, and a refreshing counter 60004, the circuit scale is increased. Moreover, since the semiconductor memory is not aimed at reduction of power consumption, it is not suited to a DMA controller of the present invention in which a memory bank is divided to reduce power consumption.
Meanwhile as the result of realizing a bulk memory area with a single DRAM in an actual LSI, there is a report as follows.
According to xe2x80x9cA Low Power MPEG-4 Video/Audio codec LSI with 16 Mbit embedded DRAM, Proceedings of COOL Chips, III, pp.89-100, April 2000xe2x80x9d, the power consumption of a 16Mbit DRAM constituted by a single macro is about 25% of 240 mw that is the power consumption of the whole LSI. Generally, as a logic part becomes smaller, the power supply voltage is reduced with relative ease, and therefore it is expected that reduction of power consumption is promoted. However, with respect to a consolidated DRAM, the voltage cannot be easily reduced due to memory cell drive. In the future, the memory capacity to be consolidated will be increased due to diversification of video applications (3D graphics, improved resolution, etc.). Accordingly, in a system LSI for which reduction of power consumption is promoted, the ratio of the power consumption of memories represented by a DRAM to the whole power consumption cannot be ignored.
The present invention is made to solve the above-described problems and has for its object to provide a high-performance DMA controller that can be easily designed with less circuit scale, and that can provide high efficiency of data transfer and low power consumption.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a high-performance DMA controller which is a data transfer controller for controlling data transfer between a main storage means holding various kinds of data, and a plurality of local storage means, and the data transfer controller comprises: an interface for generating a control signal for controlling the main storage means; a data I/O unit for controlling input and output of data; a parameter holding unit for holding various kinds of parameters that are required for execution of data transfer; a data transfer request receiver for receiving requests of data transfer; and a start command receiver for receiving a start/stop command of the data transfer controller; wherein the data transfer request receiver receives, from a data transfer request source, reservations of plural data transfer requests comprising execution priority information and local storage means type information, each information being arbitrarily set by the data transfer request source, and holds the local storage means type information in association with each execution priority information; and the data transfer controller receives only the reservations of data transfer requests until a start command is issued from a system controller for controlling the whole apparatus and, when a start command is issued from the system controller, the data transfer controller sequentially decodes the local storage means type information of the reserved data transfer requests having relatively high execution priorities, in chronological order of the data transfer requests, and then sequentially takes parameters required for data transfer from the parameter holding unit according to the decoding result, to execute data transfer. Therefore, only setting of DMA parameters and reservation of DMA transfer requests can be performed without executing data transfer.
According to a second aspect of the present invention, in the high-performance DMA controller according to the first aspect, when there are a plurality of data transfer request sources, said data transfer controller is provided with an auxiliary reservation unit for receiving reservations of data transfer requests from each of the data transfer request sources, said data transfer requests including execution priority information and local storage means type information which are arbitrarily set by the data transfer request sources; and the auxiliary reservation means transfers the data transfer requests which have been received for each of the data transfer request sources, to the data transfer request receiver, according to predetermined priorities of the data transfer request sources. Therefore, the data transfer request receiver can receive the data transfer requests that have been simultaneously outputted from the plural data transfer request sources, and reserve the data transfer requests with priorities, resulting in efficient data transfer. Further, when the circuit is altered adaptively to the plural transfer request sources, the circuit that is adapted to a single transfer request source can be reused.
According to a third aspect of the present invention, in the high-performance DMA controller according to the second aspect, one of the plural data transfer request sources is a system controller for controlling the whole system. Therefore, in programming of a processor or the like as the system controller, since initial setting for data transfer can be performed before startup of the system controller, the degree of freedom is increased, for example, an initial setting processor can be developed independently. This means that the development of the processor or the like is facilitated, leading to reduction in the period time for the development.
According to a fourth aspect of the present invention, in the high-performance DMA controller according to the second aspect, the auxiliary reservation means comprises: a plurality of auxiliary reservation registers for temporarily-holding the data transfer requests from the respective data transfer request sources; and an auxiliary selector for selecting the outputs of the data transfer requests which have temporarily been stored in the auxiliary reservation registers; and the auxiliary selector selects the data transfer requests according to the predetermined priorities of the data transfer request sources, and transfers them to the data transfer request receiver. Therefore, it is possible to control the data transfer requests that have been simultaneously outputted from the plural data transfer request sources, with a minimum of additional circuits.
According to a fifth aspect of the present invention, in the high-performance DMA controller according to any of the first, second, and fourth aspects, the data transfer request receiver comprises: a priority level decoder for decoding the execution priority information of the data transfer requests; a reservation register corresponding to each execution priority information, for holding the local storage means type information in association with each execution priority information; and a selector for selecting the outputs of the local storage means type information; and the priority level decoder stores the plural data transfer requests in the reservation registers corresponding to the respective execution priority information, and the selector selects the local storage means type information to be executed next, according to the status of a reservation flag indicating whether or not the reservation register corresponding to each execution priority information holds the reservation of the data transfer request, and transfers the selected information to the interface. Therefore, the number of registers for holding the data transfer requests can be reduced. Further, DMA transfer execution is determined on the basis of, not the priorities of all transfer types, but the transfer types in the register of the highest priority. Therefore, the priority can be determined at high speed, and control is facilitated and, moreover, the circuit is simplified. As the result, the circuit development of the high-performance DMA controller is facilitated, resulting in reduction in the
According to a sixth aspect of the present invention, in the high-performance DMA controller according to the fifth aspect, the data transfer controller determines data transfer type information to be executed next from the data transfer requests previously reserved in the reservation registers, according to the execution priority information and the times at which the transfer requests have been made, at a time a predetermined period before the end of the previous data transfer. Therefore, continuous and efficient data transfer can be performed with minimized data transfer interval by executing the preparation of data transfer execution, whereby a reservation of data transfer request of high priority, which is inputted just before data transfer, can be executed while maintaining the continuity of reservations of data transfer requests from the data transfer request source. Therefore, even when a data transfer request of higher priority is issued during execution of data transfer, data transfer can be executed in the latest order of priorities. Since control of interruption/resumption is not complicated, the circuit scale of the high-performance DMA controller is minimized, leading to reduction in the time period for development.
According to a seventh aspect of the present invention, in the high-performance DMA controller according to the sixth aspect, any of the data transfer requests includes a cancel command for canceling a data transfer request reserved in any of the reservation registers. Therefore, the reserved DMA requests can be canceled easily. Further, DMA transfer, which has become unnecessary due to the status of the system, is not carried out. Furthermore, when the canceling is combined with an operation such as re-reservation, reservations can be interexchanged. Furthermore, since unnecessary DMA transfer is not carried out, the power consumption of the high-performance DMA controller is reduced.
According to an eighth aspect of the present invention in the high-performance DMA controller according to the seventh aspect, the cancel command is effective to data transfer that is currently executed. Therefore, it is not necessary to hold parameters during halts, such as temporal stop or interruption/resumption and, further, subsequently reserved DMA transfer can be continuously executed with priority. Since this operation ensures DMA continuity even when canceling is performed, saving/re-loading cycle for interruption/resumption is not required, whereby the efficiency of the DMA transfer is not reduced.
According to a ninth aspect of the present invention, in the high-performance DMA controller according to the seventh aspect, the priority level decoder further decodes whether any of the data transfer requests includes a cancel command for canceling a data transfer request reserved in any of the reservation registers; when a cancel command is made to a reserved data transfer request, the data transfer request is canceled by changing the status of the reservation flag; and when a cancel command is made to data transfer that is currently executed, the system controller terminates the data transfer. Therefore, canceling of reservations can be performed at high speed by simple control. Further, temporal stop or interruption, which has conventionally been realized by a complicated circuit, can be realized by reservation determination timing, reservation cancel command, and re-reservation. Thereby, the high-performance DMA controller is not provided with complicated controls and needless circuits, leading to a considerable reduction in the time period for circuit design and development and the time period for verification.
According to a tenth aspect of the present invention, in the high-performance DMA controller according to the fifth aspect, the data transfer request receiver is connected to the system controller that controls the whole apparatus; and the reservation register corresponding to each execution priority information comprises a plurality of setting registers arranged in a ring shape, and a pointer register for selecting, from the plural setting registers, a setting register to be set next, and a setting register to be executed next. Therefore, it is possible to cancel the data transfer requests that have already been reserved, or interchange the priority levels of the data transfer requests, or change of the order of execution, directly from software or the like of the system controller. Further, the DMA controller can flexibly cope with various kinds of error processing and application requests, which occur during system operation, whereby the system performance is improved, resulting in a higher-performance system. Moreover, the degree of freedom in software development is increased.
According to an eleventh aspect of the present invention, in the high-performance DMA controller according to the tenth aspect, the data transfer request receiver is connected to the system controller; and the plural setting registers or the pointer register are/is arbitrarily read or written by the system controller, regardless of the data transfer requests. Therefore, setting can be speedily and arbitrarily changed directly from software or the like of the system controller. Further, it is possible to cancel the data transfer requests that have already been reserved, or interchange the priority levels of the data transfer requests, or change the order of execution. Thereby, the programmability (degree of freedom in program design) of the data transfer request source is improved, independent program designs by plural developers are facilitated. This leads to reduction in the time period for development at the data transfer request source, and increases the degree of freedom in the framework of development. Furthermore, the DMA controller can flexibly cope with various kinds of error processing and application requests, which occur during system operation, whereby the system performance is improved, resulting in a higher-performance system.
According to a twelfth aspect of the present invention, in the high-performance DMA controller according to the fifth aspect, the plural data transfer requests further include execution timing information that indicates timings to execute the data transfer requests reserved in the reservation register; and the data transfer request receiver does not execute data transfer including the execution timing information at timing other than the specified execution timing, regardless of the execution priority, add executes data transfer when the execution timing has come, according to the execution priority at that time. Therefore, delayed data transfer can be executed easily. This facilitates, for example, program design of the data transfer request source is facilitated, which program is separated into formation of a module for controlling issue of data transfer requests and formation of a processing module which does not consider data transfer. Thereby, the program development of the data transfer request source is facilitated, resulting in improvement in the efficiency of development, reduction in the time period for development, and reduction in the number of program steps.
According to a thirteenth aspect of the present invention, in the high-performance DMA controller according to the twelfth aspect, the execution timing information is the number of cycles from when a data transfer request is reserved to when the data transfer is executed; and the reservation register corresponding to each execution priority information is further provided with a reservation timer for holding the number of cycles. Therefore, execution time setting is facilitated. Thereby, delayed DMA transfer can be executed easily, and data transfer can be executed at a desired timing or when a desired time has come. As the result, development of the data transfer request source is facilitated, resulting in improvement in the efficiency of development, reduction in the time period for development, and reduction in the number of program steps.
According to a fourteenth aspect of the present invention, in the high-performance DMA controller according to the twelfth aspect, the execution timing information indicates whether a predetermined timing signal transmitted to the data transfer request receiver is to be used or not; and the reservation register corresponding to each execution priority information is further provided with a timing designation register for holding designation as to whether the timing signal is to be used or not. Therefore, the range of choices of execution methods is extended, and data transfer requests can be reserved without considering the timing to issue the data transfer requests. Thereby, the program of the data transfer request source and the request issue timing control are facilitated, and the degree of freedom in development is increased, leading to reduction in the time period for development.
According to a fifteenth aspect of the present invention, in the high-performance DMA controller according to the twelfth aspect, the execution timing information designates the type of a timing signal to be used, from plural timing signals transmitted to the data transfer request receiver; and the reservation register corresponding to each execution priority information is further provided with a timing type register for holding the type of the designated timing signal. Therefore, the degree of freedom in designation of data transfer execution timing is increased, and control for request issue timing designation by the data transfer request source is dispensed with, leading to further reduction in the load on development.
According to a sixteenth aspect of the present invention, in the high-performance DMA controller according to the twelfth aspect, the data transfer request further includes repetition information indicating the number of times the data transfer request is repeated; the data transfer request receiver is further provided with a number-of-repetition designation register for holding the repetition information, and a number-of-repetition counter for counting the number-of-repetition; and on receipt of the repetition information, the data transfer request receiver holds the reservation of the data transfer request, and when the execution timing has come, the data transfer request receiver executes the corresponding data transfer by the number of repetition times, according to the execution priority at that time. Therefore, it is not necessary for the data transfer request source to make data transfer requests of the same kind by plural times, whereby issue of requests from the data transfer request source is simplified.
According to a seventeenth aspect of the present invention, in the high-performance DMA controller according to the first aspect, the parameter holding unit has areas partitioned by addresses for each of the local storage means; and parameters to be used for data transfer corresponding to each local storage means are previously stored in each area by the system controller. Therefore, even when the DMA controller is provided with only one DMA parameter memory, information relating to plural resources can be continuously read out. Thereby, only a single command of continuous access to the parameter memory is required, whereby the program code of the data transfer request source is simplified, leading to reduction in the number of program steps and reduction in the number of execution cycles. These reductions result in improved system performance. Further, also when the execution control circuit reads data from the parameter memory, since the execution control circuit can make continuous access to the memory, preparation for data transfer can be performed at high speed and, moreover, the control circuit of the high-performance DMA controller is simplified, resulting in reduced circuit scale and reduced time period for development.
According to an eighteenth aspect of the present invention, in the high-performance DMA controller according to the first aspect, the parameter holding unit has areas partitioned by addresses for each access pattern to the main storage means; and parameters corresponding to each access pattern are previously stored in each area by the system controller. Therefore, even when the controller is provided with only one DMA parameter memory, continuous and easy access to the memory is achieved. Further, even when access to the data memory has plural access patterns, setting and readout are performed speedily and easily. Thereby, even though the controller is provided with only one DMA parameter memory, data transfer is realized in plural access methods. In this case, only a single command of continuous access to the parameter memory is required, whereby the program code of the data transfer request source is simplified, leading to reduction in the number of program steps and reduction in the number of execution cycles. As the result, the performance of the system is improved. Moreover, also when the execution control circuit reads data from the parameter memory, since the circuit can make continuous access to the memory, the control circuit of the high-performance DMA controller is simplified, leading to reduced circuit scale and reduced time period for development.
According to a nineteenth aspect of the present invention, in the high-performance DMA controller according to the first aspect, the parameter holding unit has areas partitioned by addresses for each of the local storage means, and areas partitioned by addresses for each access pattern to the main storage means; and parameters to be used for data transfer corresponding to each local storage means are previously stored in each of the areas partitioned by addresses for each local storage means, by the system controller, and parameters corresponding to each access pattern are previously stored in each of the areas partitioned by addresses for each access pattern, by the system controller. Therefore, even if the resources do not have the respective access pattern parameters, the resources can access the main memory by using the plural access patterns. Thereby, various kinds of accesses can be made to the main memory, resulting in improved system performance Furthermore, since required parameters are put together in address units, high-speed access to the parameter memory is achieved, and access control is facilitated. Furthermore, required parameters are stored in an address area corresponding to each resource and, further, required parameters are stored in an address area corresponding to each access pattern. Thereby, the parameter memory area corresponding to each resource is minimized while realizing many access patterns for each resource. This leads to reduction in the capacity of the parameter memory, reduction in the circuit scale of the high-performance DMA controller, and reduction in power consumption of the DMA controller.
According to a twentieth aspect or the present invention, in the high-performance DMA controller according to any of the seventeenth to nineteenth aspects, the parameters stored in the parameter holding means include; write/read information, access unit information, and access pattern information, corresponding to each local storage means, and a start address, the number of transfers, rectangle area access information, and start and end address information of an area forming a ring buffer, corresponding to each access pattern. Therefore, it is not necessary to specify parameters when making a data transfer request, whereby the data transfer request can be simplified and, further, many combinations of access patterns are realized. Thereby, the degree of freedom in development of the program of the processor is increased, and the program is simplified, and moreover, circuit control is facilitated, leading to reduction in the time period for development.
According to a twenty-first aspect of the present invention, in the high-performance DMA controller according to the first or second aspect, the data transfer controller further includes a clock controller for controlling supply and stop of clocks to the interface, the data I/O unit, the parameter holding means, and the main storage means; and the clock controller stops supply of clocks when the system controller does not start the data transfer controller supplies clocks when the system controller starts the data transfer controller and a data transfer request is reserved in the data transfer request receiver, stops supply of clocks when the data transfer request receiver has execution timing information, until the execution time comes, starts supply of clocks when the execution time has come, and stops supply of clocks when the reservations in the data transfer request receiver have gone and the final data transfer has ended. Therefore, the power to the high-performance DMA controller is efficiently controlled by automatically supplying the control clock relating to data transfer and the clock of the main memory only during the minimum period of time. Thereby, a system that realizes lower power consumption is obtained. Furthermore, it is not necessary for the program of the data transfer request source to perform clock control every time a data transfer request is issued and, therefore, the program is not complicated.
According to a twenty-second aspect of the present invention, in the high-performance DMA controller according to the twelfth aspect, the data transfer controller is further provided with a clock controller for controlling supply and stop of clocks to the interface, the data I/O unit, the parameter holding means, and the main storage means; the clock controller stops supply of clocks when the system controller does not start the data transfer controller, supplies clocks when the system controller starts the data transfer controller and a data transfer request is reserved in the data transfer request receiver, stops supply of clocks until the execution timing comes according to the execution timing information received by the data transfer request receiver even if the data transfer controller is started and a data transfer request is reserved, and starts supply of clocks when the execution timing has come, and stops supply of clocks when the reservations in the data transfer request receiver have gone and the final data transfer has ended. Therefore, the power to the high-performance DMA controller can be efficiently controlled by automatically supplying the clocks for a required minimum period of time. Thereby, a system that can realize lower power consumption is obtained. Further, it is not necessary for the program of the data transfer request source to perform clock control every time a data transfer request is issued. Therefore, the program is not complicated and, moreover, the number of program steps is reduced, and the number of execution cycles is reduced, resulting in improved execution performance.
According to a twenty-third aspect of the present invention, there is provided a high-performance DMA controller which is a data transfer controller for controlling data transfer between a main storage means holding various kinds of data, and a plurality of local storage means, wherein the main storage means comprises a plurality of individual main storage means that are obtained by dividing the main storage means into plural areas to which clocks are supplied independently; the data transfer controller includes a clock controller for controlling supply and stop of clocks to the main storage means and the data transfer controller, and an address decision unit for deciding an address area to access; and the clock controller supplies clocks and control signals only to the areas-to-be-used selected by the address decision unit from the plural individual main storage means, and supplies no clocks and no control signals to the unselected areas. Therefore, it is possible to operate a desired part of the main memory only for a desired period of time. Thereby, the power consumption of the circuit of the high-performance DMA controller and the power consumption of the memory are efficiently controlled, providing a system that realizes lower power consumption.
According to a twenty-fourth aspect of the present invention, there is provided a high-performance DMA controller which is a data transfer controller for controlling data transfer between a main storage means holding various kinds of data, and a plurality of local storage means, wherein the main storage means comprises a plurality of individual main storage means that are obtained by dividing the main storage means into plural areas to which clocks are supplied independently; the data transfer controller includes a clock controller for controlling supply and stop of clocks to the main storage means and the data transfer controller, and an area setting register for selecting areas-to-be-used from the individual main storage means; and the clock controller supplies clocks and control signals only to the areas-to-be-used selected by the area setting register from the plural individual main storage means, and supplies no clocks and no control signals to the unselected areas. Therefore, even when the main memory is constructed by, for example, a DRAM that is difficult to address-control, it is possible to provide a system that realizes low power consumption, by the above-mentioned simple control to the main memory, without operating unnecessary memories.
According to a twenty-fifth aspect of the present invention, in the high-performance DMA controller according to the twenty-third or twenty-fourth aspect, the data transfer controller is provided with a power supply controller for controlling supply and stop of power to the individual main storage means; and the power supply controller supplies power to only the selected areas-to-be-used, and supplies no power to the unselected areas. Therefore, current leakage from unused part of the main memory is reduced, leading to further reduction in power consumption.
According to a twenty-sixth aspect of the present invention, in the high-performance DMA controller according to the twenty-third or twenty-fourth aspect, the individual main storage means are constituted by SRAMs. Therefore, stop control can be performed utilizing addresses, and special setting means is not required, whereby the circuit of the high-performance DMA controller is simplified.
According to a twenty-seventh aspect of the present invention, in the high-performance DMA controller according to the twenty-third or twenty-fourth aspect, the individual main storage means are constituted by DRAMs, clocks and control signals are supplied to only selected DRAMs, and the selected DRAMs perform refreshing; and no clocks and no control signals are supplied to unselected DRAMs, and the unselected DRAMs do not perform refreshing. Therefore, even in a system that requires a bulk memory such as a DRAM, the power consumption of the main memory can be minimized, and supply of clocks and control signals can be easily controlled.
According to a twenty-eighth aspect of the present invention, in the high-performance DMA controller according to the twenty-third or twenty-fourth aspect, the individual main storage means are constituted by DRAMs, clocks and control signals are supplied to only selected DRAMs, and the selected DRAMs perform auto-refreshing; and no clocks and no control signals are supplied to unselected DRAMs, and the unselected DRAMs do not perform auto-refreshing but perform self-refreshing. Therefore, the power consumption can be easily reduced while maintaining the contents of the unused memory area.